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The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.cite-ref-0-1-0[1]cite-ref-1-2-0[2]

• Design

• Architecture changes in comparison with ARM Cortex-A78

• Licensing

• Usage

• See also

• References

The Cortex-X1 design is based on the ARM Cortex-A78, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).cite-ref-0-1-1[1]

The Cortex-X1 is a 5-wide decode out-of-order superscalar design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 μOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.cite-ref-2-3-0[3]cite-ref-3-4-0[4]cite-ref-4-5-0[5]cite-ref-5-6-0[6]

ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than the ARM Cortex-A77.cite-ref-2-3-1[3]cite-ref-3-4-1[4]cite-ref-4-5-1[5]cite-ref-5-6-1[6]

The Cortex-X1 supports ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with the ARM Cortex-A78 mid and ARM Cortex-A55 little cores.cite-ref-0-1-2[1]cite-ref-1-2-1[2]

• Around 20% performance improvement (+30% from A77)cite-ref-7[7]

• 30% faster integer

• 100% faster machine learning performance

• Out-of-order window size has been increased to 224 entries (from 160 entries)

• Up to 4x128b SIMD units (from 2x128b)

• 15% more silicon area

• 5-way decode (from 4-way)

• 8 MOPs/cycle decoded cache bandwidth (from 6 MOPs/cycle)

• 64 KB L1D + 64 KB L1I (from 32/64 KB L1)

• Up to 1 MB/core L2 cache (from 512 KB/core max)

• Up to 8 MB L3 cache (from 4 MB max)

The Cortex-X1 is available as SIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).cite-ref-0-1-3[1]cite-ref-1-2-2[2]

• Samsung Exynos 2100cite-ref-8[8]

• Qualcomm Snapdragon 888(+)cite-ref-9[9]

• Google Tensorcite-ref-10[10]

• ARM Cortex-A78, related high performance microarchitecture

• ARM Neoverse V1 (Zeus), server sister core to the Cortex-X1

• Comparison of ARMv8-A cores, ARMv8 family

cite-note-0-11. ↑ "Introducing the Arm Cortex-X Custom program". community.arm.com. Retrieved 2020-06-18.

cite-note-1-22. ↑ citerefltdLtd, Arm. "Cortex-X Custom CPU program". Arm | The Architecture for the Digital World. Retrieved 2020-06-18.

cite-note-2-33. ↑ citereffrumusanuFrumusanu, Andrei. "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". www.anandtech.com. Archived from the original on May 26, 2020. Retrieved 2020-06-18.

cite-note-3-44. ↑ "Arm Cortex-X1: The First From The Cortex-X Custom Program". WikiChip Fuse. 2020-05-26. Retrieved 2020-06-18.

cite-note-4-55. ↑ citerefmcgregorMcGregor, Jim. "Arm Unleashes CPU Performance With Cortex-X1". Forbes. Retrieved 2020-06-18.

cite-note-5-66. ↑ "Arm Cortex-X1 and Cortex-A78 CPUs: Big cores with big differences". Android Authority. 2020-05-26. Retrieved 2020-06-18.

cite-note-77. ↑ "Cortex-X1 – Microarchitectures – ARM – WikiChip". en.wikichip.org. Retrieved 2021-02-13.

cite-note-88. ↑ "Exynos 2100 5G Mobile Processor: Specs, Features | Samsung". Samsung Semiconductor. Retrieved 2021-01-13.

cite-note-99. ↑ "Qualcomm Snapdragon 888 5G Mobile Platform | Latest 5G Snapdragon Processor | Qualcomm". www.qualcomm.com. Retrieved 2021-01-13.

cite-note-1010. ↑ citerefamadeo2021Amadeo, Ron (2021-10-19). "The "Google Silicon" team gives us a tour of the Pixel 6's Tensor SoC". Ars Technica.